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LPDDR3 DFI Synthesizable Transactor

LPDDR3 DFI Synthesizable Transactor

LPDDR3 DFI Synthesizable Transactor provides a smart way to verify the LPDDR3 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR3 DFI Synthesizable Transactor is fully compliant with standard DFI version 3.1 or higher Specifications and provides the following features.

Features
  • Compliant with DFI version 3.1 or higher Specifications.
  • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
  • Supports for Read data-eye training.
  • Supports for Read gate training.
  • Supports for Write date-eye training.
  • Supports for CA training.
  • Supports for DFI disconnect during training.
  • Supports for write data mask and data strobe features.
  • Supports for Power Down features.
  • Supports for Deep Power Down features.
  • Supports all data rates as per specification.
  • Supports for Burst sequence.
  • Supports for Write leveling.
  • Supports for X16 and X32 mode.
  • Supports DRAM Clock disabling feature.
  • Supports Error signaling.
  • Supports all types of timing and protocol violations detection for timing parameters.
  • Protocol checker fully compliant with DFI 3.1 or higher Specifications.
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
LPDDR3 DFI Synthesizable Transactor Env

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    SmartDV's LPDDR3 DFI Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the LPDDR3 DFI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

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