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AMBA AXI4-Stream Synthesizable Transactor

AMBA AXI4-Stream Synthesizable Transactor

AMBA AXI4 Stream Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA AXI4-Stream Synthesizable Transactor is fully compliant with standard AMBA AXI4 Stream Specification and provides the following features

Features
  • Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
  • Supports AXI4-Stream Master and Slave.
  • Supports all AXI4-Stream data widths.
  • Support for all Data streams including Byte stream, Continuous aligned stream,Continuous unaligned stream and Sparse stream.
  • Support for single byte, packet and frame transfers.
  • Transfer interleaving support.
  • Support for upsizing, downsizing and merging.
  • Supports constrained randomization of protocol attributes.
  • Slave supports fine grain control of response.
  • Programmable wait states or delay insertion.
  • Ability to inject errors during transfer.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control AXI4-Stream functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus
Benefits
  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
AMBA AXI4-Stream Synthesizable Transactor Env

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    SmartDV's AMBA AXI4-Stream Synthesizable Transactor Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA AXI4-Stream Synthesizable Transactor testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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