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SmartDV offers design and verification services in the area of ASIC and FPGA design, with emphasis on quality deliverables. Our offerings are designed to function with minimal customer involvement, and the process ensures flawless and timely delivery be it designs starting from specifications or point services. SmartDV offers industry standard Verification IP like I2C, ethernet(100G/40G/10G/1G/100M), AMBA, OCP, PCIE, USB, SATA, LIN, Fiber Channel, JESD204, SATA, MIPI CSI, MIPI DSI, MIPI RFFE, MIPI HSI, MIPI Unipro, MIPI SlimBus, MIPI M-PHY, MIPI D-PHY, MIPI SPMI in Vera, E, SystemC, Verilog and SystemVerilog.
We have experience in building smart verification env in HVL like E (specman), VERA, SystemC, TestBuilder (C++), NTB, and SystemVerilog. We have vast experience in usage of building verification env with RVM, VMM, AVM, eRM, OVM, UVM
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Verification Services
SmartDV Technologies enables you to rapidly build verification environment helping you to achieve your design and verification targets through its unique blend of innovative tools and technologies. We have developed our own language and compiler, which can help write testbenches 2-4x faster than a normal verification team, compiler can generate testbench in VMM, OVM, UVM, SystemC, Specman E, Verilog. Our verification methodology helps to build highly layered, scalable, reusable and extendable verification environments for module and SOC/ASIC/FPGA/IP level verification
Our Capabilities
- Feature extraction and development of verification plan
- Development of detailed verification env document, showing all components of verification env
- Development of reusable verification environment using verification methodology like VMM, RVM, OVM and UVM in Systemverilog, Vera, SystemC, Verilog
- Development of self-checking test cases and regression suite
- Code Coverage, Functional coverage and Assertion coverage driven verification
- We have experience in writing Verification environment for very complex ASIC's (40+ Million gate design)
- We use lot of automation in writing testbenched so we can write testbenches very fast
- We have big list of Verification IP's which we can plug into any verification env and get jump start on project
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FPGA Services
SmartDV team has got vast experience with both Altera and Xilinx FPGA design from concept, design, verification, place and route to the final board design and bring-up. We have experience in FPGA prototyping of complex, multi-million ASIC's.
Our Capabilities
- Concept and feasibility study
- Cost prediction and evaluation
- System specification
- IP selection, including third party IP
- Design for testability support
- Top level and functional verification
- Hardware and software co-verification
- Synthesis, PR and Static timing analysis
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SystemVerilog Migration
SmartDV provides migration services to speed the transition from legacy languages and environments to the widely supported IEEE 1800 SystemVerilog language. SmartDV SystemVerilog migration services enable companies to easily take advantage of legacy verification environments while adopting the widely supported industry standard SystemVerilog.
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Services include translation of verification components from such as bus functional models, Assertions and random traffic generators; migration of existing test suites; and validation of migrated verification environments. These services take advantage of SmartDV's extensive verification know-how with a wide range of high-level verification languages and methodologies. We have converted Specman E to SystemVerilog, Verilog to SystemVerilog and also Vera to SystemVerilog
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