Get Smart with SmartDV, the Design and Verification IP Leader

Newsletter: Q4 2021 Issue

Welcome from Deepak Kumar Tala

Deepak Kumar Tala, Managing Director, SmartDV TechnologiesIt’s with great excitement that we put the finishing touches on this special DAC edition of our Get Smart newsletter! It’s been a long 20 months of working from home, zoom meetings and hybrid events.

Welcome back to in-person events and SmartDV. In spite of the pandemic and like many other companies, we pushed forward. We expanded our product portfolio to more than 800 different Design and Verification IP product offerings. We focused on silicon-proven, minimal-area controller Design IP for MIPI and USB interfaces targeting mobile and high-speed communications application markets.

Also, we unveiled a tool suite earlier this year that automates the protocol debugging process and testbench creation by eliminating tedious and error-prone manual approaches and improving productivity. The automation suite includes SmartViP Debug, a tool that automatically identifies protocol violations with visual and tabular views, and SmartTestBench. SmartTestBench automates the speedy creation of testbench files, either through a graphical user interface or through text files and supports a wide variety of verification scenarios.

Detecting, debugging and fixing protocol violations is a critical part of the verification flow and the most time-consuming because it typically requires detailed knowledge about the specific protocol being debugged. SmartViPDebug eliminates the need for the designer to be a protocol expert.

Our experienced R&D group understands that developing testbenches manually is tedious work and often leads to errors. In response, they developed SmartTestBench to automate the process. This powerful automation tool suite is available to our customers as a no-cost, value-added complement to our product portfolio.

Please visit us at DAC to learn more about how SmartDV’s solutions can meet your needs. Don’t miss our new video and product demos and pick up our latest datasheets and brochures.

We look forward to seeing you again at DAC 2021 and again in July 2022.

Best regards,

Deepak Kumar Tala
Managing Director


Our Technical Distinction: Spotlight on Post-Silicon Verification IP

Post-silicon verification IP (PSVIP) is growing in popularity because it offers an alternative to the familiar FPGA prototyping approach. SmartDV’s PSVIPs are configurable and reusable plug-and-play solutions to test prototype silicon, offering an efficient and high-performance platform for validating standard interface protocols such as those available from the MIPI Alliance.

Used across projects, PSVIP is a replacement for one-off, custom-built, post-silicon validation platforms often needed at the end of a design project. It is used to validate either a prototype silicon device or an FPGA platform programmed with the final design and acts as the final opportunity to validate the silicon prototype device before release to volume production.

The Verification IP (VIP) component is supplied in synthesizable RTL programmed into an FPGA that is then hardwired to either the prototype silicon DUT or to another FPGA containing the DUT. The latter approach is often used prior to silicon prototypes as a final check before committing to first silicon.

SmartDV Post-Silicon VIP

SmartDV’s PSVIP can be used for an Ethernet Controller design to provide a faster and more realistic way to validate prototype silicon or an FPGA programmed with the final design at speeds of up to 1GHz.

SmartDV offers a broad portfolio of PSVIP solutions for different protocols and can be re-used on many projects. A proprietary in-house compiler supports rapid generation and customization of PSVIP to support specific customer needs. Our PSVIP solution runs on a standard Linux or Windows platform and includes a Perl driver that communicates directly with the PSVIP instantiated in the FPGA. The PSVIP solution is offered as a Synthesizable RTL model or as a pre-programmed FPGA board with the PSVIP already built in.

Chip design verification continues to serve as the gatekeeper at each stage of the process as designs transition from a high-level description to a detailed layout of the chip. The final hurdle of the project requires verifying the prototype silicon device or an FPGA programmed with the final design before committing to volume manufacturing. This critical step is the final test to make sure that the device meets all specifications for functionality and performance before releasing the final device to production. Smart verification engineers turn to SmartDV’s reusable plug-and-play PSVIP for verification and validation of standard interface protocols.

Visit the SmartDV website to learn more about our PSVIP solutions or to see what’s new in our ever-growing IP product portfolio. Email requests for more information should be sent to


SmartDV in the News

From EEWeb: Rapid Validation of Post-Silicon Devices Using Verification IP

SmartDV Announces Reusable Plug-and-Play Validation Solution to Test Prototype Silicon


See SmartDV at ...

Design Automation Conference
December 6-8
Moscone Center West
San Francisco
Booth #2429


Connect with SmartDV at:
Twitter: @SmartDVĀ