SmartDV Newsletter: Q4 2020 Issue

Welcome from Deepak Kumar Tala

Deepak Kumar Tala, Managing Director, SmartDV TechnologiesHello and welcome to the first edition of the SmartDV newsletter, Get Smart.

2020 has been a trying year in so many ways. The semiconductor industry, however, is weathering the global challenges quite well. Many companies in this sector announced new design starts, almost all with the need for Design and Verification IP, often supplied by SmartDV. It’s with a great deal of pleasure that I look back on the year and identify a variety of new and existing market segments that we serve, including automotive, video, networking, storage, data conversion, and mobile devices.

We expanded our portfolio considerably in 2020 to more than 600 product offerings and launched a new testbench generator, SmartConf. Our Design IP solutions increased to include support for DDR5 and LPDDR5, MIPI 13C 1.1, video, imaging, and entertainment systems protocols. Our Verification IP list now adds MIPI RFFEE v3.0, Arm AMBA protocols, and MIPI A-PHY v1.0. We are usually first to market with our Design and Verification IP because of our proprietary, automated compiler-based technology that allows us to rapidly generate or modify IP. It also ensures our IP is compliant with standard protocol specifications for new or evolving applications. Finally, I’m happy to announce that we have partnered with Aldec to link our Verification IP with Aldec’s Riviera-PRO simulator, thus broadening our support for industry platforms.

We’re proud that engineers like you rely on SmartDV for your Design and Verification IP, using it through the design and verification processes from design IP through SoC verification to post-silicon validation. You have our ongoing commitment to support you and rapidly customize Design and Verification IP for your specific applications and requirements.

Please enjoy the newsletter and give us your feedback. Comments, suggestions, and questions are invited.

Best regards,

Deepak Kumar Tala
Managing Director

For more from Deepak, see his interview in SemiWiki:


Our Technical Distinction: Spotlight on our SmartDV Compiler

Our newer customers are often surprised to find that SmartDV’s portfolio of IP includes more than 600 distinct products and that we are usually the first-to-market when new protocols are announced.

How does SmartDV create, support, and maintain so many different IP products?

SmartDV SmartCompiler

Our proprietary in-house SmartDV Compiler allows us to rapidly create and customize IP. Early on, our founders invested in developing compiler technology that would allow them to compete effectively with larger vendors with many more resources. Over the years, the SmartDV Compiler has constantly evolved and improved and along with it, SmartDV’s IP portfolio has grown.

The compiler supports the creation of Verification IP, Synthesizable Transactors, Design IP, and Memory Models. Based on a proprietary high-level language and parameters that are input into the compiler it produces high-quality and consistent code. Iterating IP for new releases or customization, based on customer demand, is fast and automated. This approach is superior to typical manual efforts where quality can vary significantly and more cost effective as fewer resources are needed to create a large volume of IP. The SmartDV Compiler is truly a one-of-a-kind code generator.

In addition to generating IP code, the compiler automatically outputs about 80% of the documentation required to ship with the IP. It also generates makefiles, scripts, IP-XACT files, reports, and other necessary files and information required to support the IP.

Since we develop both Verification IP and Design IP, we are often asked about our methodology for ensuring the quality of both. SmartDV maintains separate teams for developing Verification IP and Design IP. No code is shared between the groups –– high-level input code is developed separately by each group to avoid having an inadvertent error in the Verification IP from being replicated in the Design IP or vice versa. 

Once the Verification IP and Design IP are created by separate teams, they cross-verify both against each other and then review and correct, as needed. Cross-product regressions are put in place to support the IP going forward and ensure they remain synchronized. Design IP is additionally verified via FPGA and/or by outside third parties.

Our investment in the SmartDV Compiler technology benefits you in several ways. When a new protocol is announced and available, SmartDV can quickly deliver IP to support it. As the protocol evolves over time and is upgraded or revised, we respond quickly.

From your feedback, our ability to modify our IP for your specific needs or customizations is what you value most. Using the SmartDV Compiler, we can turn around customization requests in just a few days or weeks – quite different than the market norm of months.

Visit the SmartDV website to see what’s new in our IP product line.


SmartDV in the News


Bipul Talukdar, Director of Applications Engineering for North America, SmartDV TechnologiesBipul Talukdar is our Director of Applications Engineering for North America, for those of you who haven’t met him yet. He is also our resident expert on verification and RISC-V, and regularly contributes to the industry discussion. Here are a few of his recent articles:

The Future of Chip Design

The Thriving Silicon IP Business
RISC-V’s CPU Verification Challenge

Semiconductor Digest:
TileLink Verification IP to Accelerate RISC-V Design Verification Signoff

Electronic Design:
11 Myths About Verification IP

Embedded Computing Design:
Verification IP: A Vital Component of Chip Design Verification

Upcoming Events

Virtual RISC-V Summit
December 8-10
Use code SMARTDV for 25% off registration

See us at the RISC-V Summit next week! Schedule virtual meetings to learn more about our Design and Verification IP solutions and how they enable users to get to market quickly and confidently. Schedule in our RISC-V Summit Virtual Booth or via email at

Tech Talk with SmartDV: SmartDV’s RISC-V Solutions
Wednesday, December 9, 2020 1:50 PM to 2:00 PM
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV

December 10
Chongqing, China

See SmartDV at the RISC-V Summit


Connect with SmartDV at:
Twitter: @SmartDV