SERIAL_FLASH CONTROLLER interface provides full support for the two-wire SERIAL FLASH CONTROLLER synchronous serial interface,compatible with SERIAL FLASH specification. Through its SERIAL FLASH CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. SERIAL FLASH CONTROLLER IIP is proven in FPGA environment.The host interface of the SERIAL FLASH CONTROLLER can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Serial Flash Controller IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with Flash Devices from major Flash Device Vendors
- Full SPI Master Functionality.
- Supports Single, Dual, Quad, Octal SPI data widths SOC Master and SOC Slave bus can be APB/AHB/AXI/OCP/Tilelink/Wishbone/VCI/PLB/Avalon or any other protocol listed above.
- Supports 3 modes of operation
- Slave Mode – Accessing flash device through CSR registers from SOC Slave interface
- XIP Mode – eXecute In-Place, where core allows direct access to flash memory from SOC Slave interface.
- HCI Mode – Descriptor based DMA type access from SOC Master interface
- Programmable Command Sequence when working in slave mode
- Supports xSPI (JEDEC’s JESD251), Xccela and Optional Hyperbus standard
- Supports up to 4 Devices (Can be customized for more devices).
- Individually Controllable pins to drive chip-select, write protect and hold signal.
- Extended Address for Access to higher memory density.
- DDR (Double Data Rate) support.
- Advanced Sector Protection.
- Direct Memory Access (DMA) support with Host Controller Interface (HCI)
- Boot image copy Support after power on reset.
- Thresholds to generate interrupt.
- Control and Status Registers to configure the modules.
- Configurable Transmit/Receive Data FIFO.
- Software and Hardware Reset.
- Fully synthesizable.
- Static synchronous design.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's SERIAL FLASH CONTROLLER IP contains following
- The SERIAL FLASH CONTROLLER interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
