HDCP 2.3 Receiver core is compliant with standard HDCP specification as 2.2 and 2.3. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. HDCP 2.3 Receiver IIP is proven in FPGA environment. The Receiver interface of the HDCP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
HDCP 2.3 RECEIVER IIP is supported natively in Verilog and VHDL
- Features
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- Supports HDCP version 2.2 and 2.3 Specifications.
- User keys can be loaded for Authentication.
- Cipher text can be generated using Hardware/API for Authentication Protocol.
- Supports Authentication Protocols.
- Authentication and Key Exchange
- Locality Check
- Session Key Exchange
- Link Integrity Check
- Key Derivation
- Supports System Renewability Message (SRM) and Revocation.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's HDCP Receiver IP contains following
- The HDCP Receiver interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
