GDDR6 interface provides full support for the GDDR6 interface, compatible with standard JESD250, JESD250A and JESD250B specification with version 3.11 and DFI-version 4.0 or 5.0 Specification Compliant. Through its GDDR6 compatibility, it provides a simple interface to a wide range of low-cost devices. GDDR6 IIP is proven in FPGA environment. The host interface of the GDDR6 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
GDDR6 Controller IIP is supported natively in Verilog and VHDL
- Features
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- Supports GDDR6 protocol standard JESD250, JESD250A and JESD250B specification with version 3.11.
- Compliant with DFI-version 4.0 or 5.0 Specification.
- Supports all the GDDR6 commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
- Supports controllable outstanding transactions for AXI write and read channels
- Supports in port arbitration and multi port arbitration.
- Supports user programmable page policy.
- Closed page policy
- Open page policy
- Supports Error Checking and correction (ECC).
- Supports retry on ECC error, with retry limit user controllable.
- Supports high clock speeds in ASIC and FPGA.
- Supports low latency for write and read path.
- Supports reordering of transactions for higher performance.
- Supports 2 separate independent channels with point-to-point interface for data, address and command.
- Supports Double Data Rate (DDR) or Quad Data Rate (QDR) data.
- Supports Pseudo channel mode operation.
- Supports up to 32GB device density.
- Supports X8 and X16 Mode.
- Supports Programmable READ/WRITE latency.
- Supports Bank grouping and 16 internal banks per channel.
- Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
- Supports Read/Write data transmission integrity secured by cyclic redundancy check.
- Supports Input/output PLL/DLL on/off mode.
- Supports READ/WRITE EDC on/off mode.
- Supports WRITE Data mask function (single/double byte mask).
- Supports Programmable EDC hold pattern for CDR.
- Supports Programmable CRC READ/WRITE latency.
- Supports Low Power modes.
- Supports Refresh Management (RFM).
- Supports Auto refresh & self-refresh modes.
- Supports On-die termination operation.
- Supports Vendor ID1 and ID2 for identification.
- Supports COMMAND ADDRESS, WCK2CK,READ/WRITE Training mode’s.
- Supports IEEE.1149.1 boundary scan operation.
- Supports programmable clock frequency of operation.
- Supports all mode registers programming.
- Supports for power down features.
- Supports for input clock stop and frequency change.
- Fully synthesizable
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's GDDR6 IP contains following
- The GDDR6 interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
