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FEC RS (198,194) IIP

FEC RS (198,194) IIP

FEC RS (198,194) core is compliant with standard Universal Serial Bus 4 Specification and standard VESA Display Port version 2.0/2.1 Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (198,194) IIP is proven in FPGA environment.

FEC RS (198,194) IIP is supported natively in Verilog and VHDL

Features
  • Supports the Universal Serial Bus 4 Specification and VESA Display Port version 2.0/2.1 Specification.
  • Supports full FEC functionality.
  • Supports Reed Solomon (198,194) FEC, 8-bit symbols.
  • Supports the input and output data widths of multiples of 8-bit.
  • Supports the parity generation of 32 bits.
  • Supports the bit locker mechanism.
  • Supports the Syndrome calculation.
  • Supports the Berlekamp's algorithm.
  • Supports the Chien search for error position.
  • Supports the Error correction of 16 bits.
  • Supports up to the 2 symbols of error correction.
  • Supports the pipelined mechanism for the error correction.
Benefits
  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    SmartDV's FEC RS (198,194) IP contains following

  • The FEC RS (198,194) interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • Documentation contains User's Guide and Release notes.

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