Ethernet 10G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 10G MAC IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses
ETHERNET 10G MAC IIP is supported natively in Verilog and VHDL
- Features
-
- Compliant with IEEE Standard 802.3-2018 specification
- Supports full duplex mode of operation
- Supports Standard 10Gbps Ethernet link layer data
- Supports XGMII interface operating at 156.23MHz
- Supports Programmable Inter Packet Gap(IPG) and Preamble length
- Supports MDIO (Clause 22 and Clause 45) Interface
- Supports start control character alignment
- Provides detailed statistics as per the specification
- Supports Jumbo Frame
- Supports Loopback functionality
- Supports transmit and receive FIFO interface
- Supports FCS(CRC) transmission and reception
- Supports Pause frame based flow control
- Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
- Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
- Optional Wake-on-LAN support
- Supports AXI stream Interface for System Interface
- In house UNH compliance tested
- Optional support for TCP/IP offload
- Optional support for IEEE Standard 1588-2008 PTP
- Optional support for DMA on both transmit and receive side
- Optional support for the following HiGig features
- HiGig
- HiGig+
- HiGig2
- HiGigLite
- 2.5G HiGig
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
-
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's Ethernet 10G MAC IP contains following
- The Ethernet interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
