AMBA AXI5-Lite Assertion IP provides an smart way to verify the ARM AMBA AXI5-Lite component of a SOC or a ASIC. The SmartDV's AMBA AXI5-Lite Assertion IP is fully compliant with standard AMBA AXI5-Lite Specification and provides the following features.
AMBA AXI5-Lite Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA AXI5-Lite Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with the latest ARM AXI5-Lite Protocol Specification.
- Supports all AXI5-Lite data and address widths.
- Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
- Separate address, data and response phases. Separate read and write channels.
- Support for burst-based transactions with only start address issued.
- Write strobe support.
- Narrow transfer support.
- Unaligned address access support.
- Protected accesses with normal/privileged, secure/non-secure and data/instruction.
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Supports unmapped region address accesses.
- AWCACHE and ARCACHE Attributes.
- AXI5-Lite specific features
- All transactions burst length 1.
- Reordering of responses for requests with different IDs.
- All accesses Device Non-bufferable.
- Atomic access support with normal access.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV AXI5-Lite VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure AXI5-Lite Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA AXI5-Lite Assertion Env
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SmartDV's AMBA AXI5-Lite Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
