ONFi

ONFi

ONFi (Open Nand Flash Interface) provides an smart way to verify the ONFi host controller or ONFI Flash memory model of a SOC or a ASIC. The SmartDV's ONFi is fully compliant with standard ONFi Specification and provides the following features.

ONFi is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Features

• Compliant with ONFi 3.0 specifiecation.
• Supports Source Synchronous and Asynchronous data interfaces.
• Supports all mandatory and optional commands.
• Supports 16 bit bus width operations
• Multiple LUN Operation support.
• Multi-plane commands support.
• Configurable timing modes for Source Synchronous and Asynchronous data interface.
• Supports Partial Page programming.
• Source Synchronous data interface supports Clock Stop feature.
• Supports dual data bus.
• Supports Small Data Move command for both Program and Copyback operations.
• Ability to generate Vendor Specific Commands and Block Abstracted NAND Commands.
• Rich set of configuration parameters to control ONFi functionality.
• Supports constrained randomization of protocol attributes.
• On-the-fly protocol and data checking.
• Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Status counters for various events on bus.
• Callbacks in host, slave and monitor for user processing of data.
• ONFI Verification IP comes with complete testsuite to test every feature of ONFI specification.
• Functional coverage for complete ONFi features.

Benefits

• Faster testbench development and more complete verification of ONFi designs.
• Easy to use command interface simplifies testbench control and configuration of Host and Slave.
• Simplifies results analysis.
• Runs in every major simulation environment.

ONFi Verification Env

SmartDV's ONFi Verification env contains following.

• Complete source code of ONFi master and monitor
• Complete regression suite containing all the ONFi testcases.
• Examples's showing how to connect various components, and usage of Host, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.

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